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rev. a a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 ad8304 160 db range (100 pa ?0 ma) logarithmic converter features optimized for fiber optic photodiode interfacing eight full decades of range law conformance 0.1 db from 1 na to 1 ma single-supply operation (3.0 vC 5.5 v) complete and temperature stable accurate laser-trimmed scaling: logarithmic slope of 10 mv/db (at vlog pin) basic logarithmic intercept at 100 pa easy adjustment of slope and intercept output bandwidth of 10 mhz, 15 v/ s slew rate 1-, 2-, or 3-pole low-pass filtering at output miniature 14-lead package (tssop) low power: ~4.5 ma quiescent current (enabled) applications high accuracy optical power measurement wide range baseband log compression versatile detector for apc loops functional block diagram 6 3 4 pdb bias vref 10 2 12 i pd vpdb vsum inpt vsum 5 1 vneg ~ 10k a com 14 vps2 pwdn vps1 vref 7 vlog 8 bfin 9 bfng 13 temperature compensation 5k 11 v out 0.5v ad8304 product description the ad8304 is a monolithic logarithmic detector optimized for the measurement of low frequency signal power in fiber optic systems. it uses an advanced translinear technique to provide an exceptionally large dynamic range in a versatile and easily used form. its wide measurement range and accuracy are achieved using proprietary design techniques and precise laser trimming. in most applications only a single positive supply, v p , of 5 v will be required, but 3.0 v to 5.5 v can be used, and certain appli cations benefit from the added use of a negative supply, v n . when using low supply voltages, the log slope is readily altered to fit the available span. the low quiescent current and chip disable features facilitate use in battery-operated applica tions. the input current, i pd , flows in the collector of an optimally scaled npn transistor, connected in a feedback path around a low offset jfet amplifier. the current-summing input node operates at a constant voltage, independent of current, with a default value of 0.5 v; this may be adjusted over a wide range, including ground or below, using an optional negative supply. an adaptive biasing scheme is provided for reducing the dark current at very low light input levels. the voltage at pin vpdb applies approximately 0.1 v across the diode for i pd = 100 pa, rising linearly with current to 2.0 v of net bias at i pd = 10 ma. the input pin inpt is flanked by the guard pins vsum that track the voltage at the summing node to minimize leakage. the default value of the logarithmic slope at the output vlog is accurately scaled to 10 mv/db (200 mv/decade). the resistance at this output is laser-trimmed to 5 k ? , allowing the slope to be lowered by shunting it with an external resistance; the addition of a capacitor at this pin provides a simple low-pass filter. the intermediate voltage vlog is buffered in an output stage that can swing to within about 100 mv of ground (or v n ) and the posi- tive supply, v p , and provides a peak current drive capacity of 20 ma. the slope can be increased using the buffer and a pair of external feedback resistors. an accurate voltage reference of 2v is also provided to facilitate the repositioning of the intercept. many operational modes are possible. for example, low-pass filters of up to three poles may be implemented, to reduce the output noise at low input currents. the buffer may also serve as a com- parator, with or without hysteresis, using the 2 v reference, for example, in alarm applications. the incremental bandwidth of a translinear logarithmic amplifier inherently diminishes for small input currents. at the 1 na level, the ad8304 s bandwidth is about 2 khz, but this increases in proportion to i pd up to a maximum value of 10 mhz. the ad8304 is available in a 14-lead tssop package and specified for operation from C 40 c to +85 c.
rev. a C2C ad8304?pecifications (v p = 5 v, v n = 0 v, t a = 25 c, unless otherwise noted.) parameter conditions min 1 typ max 1 unit input interface pin 4, inpt; pin 3 and pin 5, vsum specified current range flows toward inpt pin 100 pa 10 ma input node voltage internally preset; may be altered 0.46 0.5 0.54 v temperature drift C 40 c < t a < +85 c 0.02 mv/ c input guard offset voltage v in C v sum C 20 +20 mv photodiode bias 2 established between pin 6, v pdb , and pin 4 minimum value i pd = 100 pa 70 100 mv transresistance 200 mv/ma logarithmic output pin 8, vlog slope laser-trimmed at 25 c 196 200 204 mv/dec 0 c < t a < 70 c 194 207 mv/dec intercept laser-trimmed at 25 c60 100 140 pa 0 c < t a < 70 c35 175 pa law conformance error 10 na < i pd < 1 ma, peak error 0.05 0.25 db 1 na < i pd < 1 ma, peak error 0.1 0.7 db maximum output voltage 1.6 v minimum output voltage limited by v n = 0 v 0.1 v output resistance laser-trimmed at 25 c 4.95 5 5.05 k ? reference output pin 7, vref voltage wrt ground laser-trimmed at 25 c 1.98 2 2.02 v C 40 c < t a < +85 c 1.92 2.08 v output resistance 2 ? output buffer pin 9, bfin; pin 13, bfng; pin 11, vout input offset voltage C 20 +20 mv input bias current flowing out of pin 9 or pin 13 0.4 a incremental input resistance 35 m ? output range r l = 1 k ? to ground v p C 0.1 v output resistance 0.5 ? wide-band noise 3 i pd > 1 a (see typical performance characteristics) 1 v/ hz small signal bandwidth 3 i pd > 1 a (see typical performance characteristics) 10 mhz slew rate 0.2 v to 4.8 v output swing 15 v/ s power-down input pin 2, pwdn logic level, hi state C 40 c < t a < +85 c, 2.7 v < v p < 5.5 v 2 v logic level, lo state C 40 c < t a < +85 c, 2.7 v < v p < 5.5 v 1 v power supply pin 10 and pin 12, vps1 and vps2; pin 1, vneg positive supply voltage 3.0 5 5.5 v quiescent current 4.5 5.3 ma in disabled state 60 a negative supply voltage 4 |1v p C v n | < 8v 0 C 5.5 v notes 1 minimum and maximum specified limits on parameters that are guaranteed but not tested are six sigma values. 2 this bias is internally arranged to track the input voltage at inpt; it is not specified relative to ground. 3 output noise and incremental bandwidth are functions of input current; see typical performance characteristics. 4 optional speci ? cations subject to change without notice.
rev. a ad8304 C3C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8304 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings * supply voltage v p C v n . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 v input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ma internal power dissipation . . . . . . . . . . . . . . . . . . . . 270 mw ja . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c/w maximum junction temperature . . . . . . . . . . . . . . . . 125 c operating temperature range . . . . . . . . . . . C 40 c to +85 c storage temperature range . . . . . . . . . . . . C 65 c to +150 c lead temperature range (soldering 60 sec) . . . . . . . . 300 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. pin function descriptions pin no. mnemonic function 1 vneg optional negative supply, v n . this pin is usually grounded; for details of usage, see applications section. 2p wdn power-down control input. device is active when pwdn is taken low. 3, 5 vsum guard pins. used to shield the inpt current line. 4i npt photodiode current input. usually connected to photodiode anode (the photo current flows toward inpt). 6 vpdb photodiode biaser output. may be connected to photodiode cathode to provide adaptive bias control. 7 vref voltage reference output of 2 v 8 vlog output of the logarithmic front-end processor; r out = 5 k to ground. 9 bfin buffer amplifier noninverting input (high impedance) 10 vps2 positive supply, v p (3.0 v to 5.5 v) 11 vout buffer output; low impedance 12 vps1 positive supply, v p (3.0 v to 5.5 v) 13 bfng buffer amplifier inverting input 14 acom analog ground pin configuration top view (not to scale) ad8304 vneg pwdn vsum inpt vsum vpdb vref a com bfng vps1 v out vps2 bfin vlog 1 2 3 4 5 6 7 14 13 12 11 10 9 8 ordering guide model temperature range package description package option ad8304aru C 40 c to +85 ct ube, 14-lead tssop ru-14 ad8304aru-reel 13" tape and reel ad8304aru-reel7 7" tape and reel AD8304-EVAL evaluation board
rev. a C4C ad8304?ypical performance characteristics 1.6 0 v log ?v 1.4 0.8 0.6 0.4 0.2 1.2 1.0 ?0 c +25 c +85 c input ?a 100p 10m 1n 10n 100n 1 10 100 1m t a = ?0 c, +25 c, +85 c v n = ?.5v 0 c +70 c tpc 1. v log vs. i pd input ?a 2.0 ?.0 100p 10m 1n error ?db (10mv/db) 10n 100n 1 10 100 1m 1.5 0 ?.5 ?.0 ?.5 1.0 0.5 +25 c ?0 c t a = ?0 c, +25 c, +85 c v n = ?.5v 0 c +70 c +85 c tpc 2. logarithmic conformance (linearity) for v log 2.0 ?.0 error from ideal output ?db (10mv/db) 1.5 0 ?.5 ?.0 ?.5 1.0 0.5 5.5v 5.0v 4.5v input ?a 100p 10m 1n 10n 100n 1 10 100 1m v p = 4.5v, 5.0v, 5.5v v n = ?.1v tpc 3. absolute deviation from nominal speci- fied value of v log for several supply voltages 0.510 v sum ?v 0.508 0.502 0.500 0.506 0.504 +85 c +25 c ?0 c input ?a 100p 10m 1n 10n 100n 1 10 100 1m t a = ?0 c, +25 c, +85 c tpc 4. v sum vs. i pd input ?ma 2.8 1.4 0.6 010 1 v pdb ?v 23456 789 2.6 1.6 1.2 0.8 2.0 1.8 1.0 2.4 2.2 ?0 c +25 c +85 c t a = ?0 c, +25 c, +85 c tpc 5. v pdb vs. i pd input ?a 2.4 0.6 100p 10m 1n v out ?v 10n 100n 1 10 100 1m 2.2 1.6 1.4 1.2 1.0 2.0 1.8 +85 c +25 c ?0 c 0.8 1.25 ?.00 error ?db (10mv/db) 1.00 0.25 0 ?.25 ?.50 0.75 0.50 ?.75 t a = ?0 c, +25 c, +85 c v p = 3.0v tpc 6. logarithmic conformance (linearity) for a 3 v single supply (see figure 6) (v p = 5 v, v n = 0 v, t a = 25 c, unless otherwise noted.)
rev. a ad8304 C5C frequency ?hz 10 ?0 ?0 100 100m 1k normalized response ?db 10k 100k 1m 10m ?0 ?0 ?0 0 ?0 ?0 1na 10na 1 a 10 a 10ma 100 a 1ma 100na tpc 7. small signal ac response, i pd to v log (5% sine modulation of i pd at frequency) i pd ? a 100 10 0.01 v rms/ hz 1 0.1 10khz 100khz 100hz 1khz 1mhz 10m 100n 10 1n 10n 1 100 1m tpc 8. spot noise spectral density at v log vs. i pd frequency ?hz 100 1 0.01 100 10m 1k v rms/ hz 10k 100k 1m 10 0.1 1na 10na 100na 1 a 10 a > 100 a tpc 9. spot noise spectral density at v log vs. frequency 0 10 5 input current ?a 10m 100n 10 1n 10n 1 100 1m wideband noise ?mv rms 9 8 7 6 4 3 2 1 tpc 10. total wideband noise voltage at v log vs. i pd frequency ?hz 3 0 ?2 100 100m 1k normalized response ?db 10k 100k 1m 10m ? ? ? a v = 5 a v = 2.5 a v = 2 a v = 1 gain = 1 , 2 , 2.5 , 5 tpc 11. small signal response of buffer frequency ?hz 10 0 ?0 10 100k 100 normalized gain ?db 1k 10k ?0 ?0 ?0 ?0 ?0 ?0 f c = 1khz tpc 12. small signal response of buffer operating as two-pole filter
rev. a C6C ad8304 input ?a 2.0 ?.0 100p 10m 1n error ?db (10mv/db) 10n 100n 1 10 100 1m 1.5 0 ?.5 ?.0 ?.5 1.0 0.5 t a = 25 c mean + 3 mean ?3 tpc 13. logarithmic conformance error distribution (3 to either side of mean) input ?a 5 ? 100p 10m 1n error ?db (10mv/db) 10n 100n 1 10 100 1m 4 1 0 ? ? 3 2 ? ? t a = 0 c, 70 c mean + 3 @ 70 c mean ?3 @ 70 c mean 3 @ 0 c tpc 14. logarithmic conformance error distribution (3 to either side of mean) input ?a 5 ? 100p 10m 1n error ?db (10mv/db) 10n 100n 1 10 100 1m 4 1 0 ? ? 3 2 ? ? t a = 40 c, 85 c mean 3 @ 40 c mean 3 @ 40 c mean 3 @ 85 c tpc 15. logarithmic conformance error distribution (3 to either side of mean) temperature ? c 20 ?5 ?0 ?0 90 ?0 v ref drift ?mv ?0 ?0 0 10 20 40 60 80 15 ?0 ?0 0 ? ?5 10 5 30 50 70 mean + 3 mean ?3 tpc 16. v ref drift vs. temperature (3 to either side of mean) temperature ? c 3 ? ? ?0 90 ?0 slope change from 25 c ?mv/dec ?0 ?0 0 10 20 40 60 80 2 ? ? ? 1 0 30 50 70 mean + 3 mean ?3 tpc 17. slope drift vs. temperature (3 to either side of mean) temperature ? c 40 ?0 ?0 ?0 90 ?0 intercept change from 25 c ?pa ?0 ?0 0 10 20 40 60 80 30 ?0 ?0 0 ?0 20 10 30 50 70 mean + 3 mean ?3 tpc 18. intercept drift vs. temperature (3 to either side of mean)
rev. a ad8304 C7C temperature ? c 8 ? ?0 90 ?0 v os drift ?mv ?0 ?0 0 10 20 40 60 80 6 ? 0 ? 4 2 30 50 70 mean + 3 mean ?3 tpc 19. output buffer offset vs. temperature (3 to either side of mean) logarithmic slope ?mv/dec 180 160 0 196 204 198 hits 200 202 100 60 40 20 140 120 80 tpc 20. distribution of logarithmic slope, sample 1000 logarithmic intercept ?pa 160 0 60 140 80 hits 100 120 100 60 40 20 140 120 80 tpc 21. distribution of logarithmic intercept, sample 1000 input guard offset ?mv 180 0 ?0 20 ?0 hits 010 100 60 40 20 140 120 80 160 tpc 22. distribution of input guard offset voltage (v inpt C v sum ), sample 1000
rev. a C8C ad8304 basic concepts the ad8304 uses an advanced circuit implementation that exploits the well known logarithmic relationship between the base-to-emitter voltage, v be , and collector current, i c , in a bipolar transistor, which is the basis of the important class of translinear circuits * : vv ii be t c s = log( / ) (1) there are two scaling quantities in this fundamental equation, namely the thermal voltage v t = kt/q and the saturation current i s . these are of key importance in determining the slope and intercept for this class of log amp. v t has a process-invariant value of 25.69 mv at t = 25 c and varies in direct proportion to absolute tempera ture, while i s is very much a process- and device-dependent parameter, and is typically 10 C 16 a at t = 25 c but exhibits a huge variation over the temperature range, by a factor of about a billion. while these variations pose challenges to the use of a transistor as an accurate measurement device, the remarkable matching and isothermal properties of the components in a monolithic process can be applied to reduce them to insignificant proportions, as will be shown. logarithmic amplifiers based on this unique property of the bipolar transistor are called translinear log amps to distin- guish them from other analog devices products designed for rf applications that use quite different principles. the very strong temperature variation of the saturation current i s is readily corrected using a second reference transistor, having an identical variation, to stabilize the intercept. similarly, pro pri- etary techniques are used to ensure that the logarithmic slope is temperature-stable. using these p rinciples in a carefu lly scaled design, the now accurate relationship between the input current, i pd , applied to pin inpt, and the voltage appearing at the inter- mediate output pin vlog is: vv ii log y pd z = log ( / ) 10 (2) v y is called the slope voltage (in the case of base-10 logarithms, it is also the volts per decade ). the fixed current i z is called the intercept. the scaling is chosen so that v y is trimmed to 200 mv/decade (10 mv/db). the intercept is positioned at 100 pa; the output voltage v log would cross zero when i pd is of this value. however, when using a single supply the actual v log must always be slightly above ground. on the other hand, by using a negative supply, this voltage can actually cross zero at the intercept value. using equation 2, one can calculate the output for any value of i pd . thus, for an input current of 25 na , vvna pa v log == 02 25 100 0 4796 10 . log ( / ) . (3) in practice, both the slope and intercept may be altered, to either higher or lower values, without any significant loss of calibration accuracy, by using one or two external resistors, often in conjunc- tion with the trimmed 2 v voltage reference at pin vref. optical measurements when interpreting the current i pd in terms of optical power inci- dent on a photodetector, it is necessary to be very clear about the transducer properties of a biased photodiode. the units of this transduction process are expressed as amps per watt. the param- eter , called the photodiode responsivity, is often used for this purpose. for a typical ingaas p-i-n photodiode, the responsivity is about 0.9 a/w. it is also important to note that amps and watts are not usually related in this proportional manner. in purely electrical circuits, a current i pd applied to a resistive load r l results in a power proportional to the square of the current (that is, i pd 2 r l ). the reason for the difference in scaling for a photodiode interface is that the current i pd flows in a diode biased to a fixed voltage, v pdb . in this case, the power dissipated within the detector diode is simply proportional to the current i pd (that is, i pd v pdb ) and the proportionality of i pd to the optical power, p opt , is preserved. ip pd opt = (4) accordingly, a reciprocal correspondence can be stated between the intercept current, i z , and an equivalent intercept power, p z , thus: ip zz = (5) and equation 2 may then be written as: vv pp log y opt z = log ( / ) 10 (6) for the ad8304 operating in its default mode, its i z of 100 pa corresponds to a p z of 110 picowatts, for a diode having a responsivity of 0.9 a/w. thus, an optical power of 3 mw would generate: vvmw pw v log == 02 3 110 1 487 10 . log ( / ) . (7) note that when using the ad8304 in optical applications, the interpretation of v log is in terms of the equivalent optical power, the logarithmic slope remains 10 mv/db at this output. this can be a little confusing since a decibel change on the optical side has a different meaning than on the electrical side. in either case, the logarithmic slope can always be expressed in units of mv per decade to help eliminate any confusion. decibel scaling in cases where the power levels are already expressed as so many decibels above a reference level (in dbm, for a reference of 1 mw), the logarithmic conversion has already been performed, and the log ratio in the above expressions becomes a simple differ- ence. one needs to be careful in assigning variable names here, because p is often used to denote actual power as well as this same power expressed in decibels, while clearly these are num eri- cally different quantities. such potential misunderstandings can be avoided by using d to denote decibel powers. the quantity v y ( volts per decade ) must now be converted to its decibel value, v y = v y /10, be cause t here are 10 db per decade in the context of a power measurem ent. then it can be stated that: vddmvdb log opt z =? () 20 / (8) where d opt is the optical power in decibels above a reference level, and d z is the equivalent intercept power relative to the same level. this convention will be used throughout this data sheet. * for a basic discussion of the topic, see translinear circuits: an historical overview, b. gilbert, analog integrated circuits and signal processing , 9, pp. 95 C 118, 1996.
rev. a ad8304 C9C to repeat the previous example: for a reference power level of 1 mw, a p opt of 3 mw would correspond to a d opt of 10 log 10 (3) = 4.77 dbm, while the equivalent intercept power of 110 pw will correspond to a d z of C 69.6 dbm; now using equation 8: vmv v log = {} = 20 4 77 69 9 1 487 . C ( C .) . (9) which is in agreement with the result from equation 7. general structure the ad8304 addresses a wide variety of interfacing conditions to meet the needs of fiber optic supervisory systems, and will also be useful in many nonoptical applications. these notes explain the structure of this unique translinear log amp. f igure 1 is a simplified schematic showing the key elements. photodiode input current i pd inpt ~ 10k c1 r1 vneg (normally grounded) i ref (internal) 0.5v q1 q2 qm intercept and temperature compensation (subtract and divide by t k) vsum 0.6v 0.5v 0.5v v be1 v be2 200 v pdb vpdb v be1 v be2 296mvp a com vlog v log 40 a/dec 5k figure 1. simplified schematic the photodiode current i pd is received at input pin inpt. the summing voltage at this node is essentially equal to that on the two adjacent guard pins, vsum, due to the low offset voltage of the ultralow bias j-fet op amp used to support the operation of the transistor q1, which converts the current to a logarithmic voltage, as delineated in equation 1. vsum is needed to provide the collector-emitter bias for q1, and is internally set to 0.5 v, using a quarter of the reference voltage of 2 v appearing on pin vref. in conventional translinear log amps, the summing node is gener- ally held at ground potential, but that condition is not readily realized in a single-supply part. to address this, the ad8304 also supports the use of an optional negative supply voltage, v n , at pin vneg. for a v n of at least C 0.5 v the summing node can be connected to ground potential. larger negative voltages may be used, with essentially no effect on scaling, up to a maximum supply of 8 v between vpos and vneg. note that the resistance at the vsum pins is approximately 10 k ? to ground; this voltage is not intended as a general bias source. the input-dependent v be of q1 is compared with the fixed v be of a second transistor, q2, which operates at an accurate internally generated current, i ref = 10 a. the overall intercept is arranged to be 100,000 times smaller than i ref , in later parts of the signal chain. the difference between these two v be values can be written as vv kt qii be be pd ref 12 C / log ( / ) = 10 (10) thus, the uncertain and temperature-dependent saturation current, i s that appears in equation 1, has been eliminated. next, to eliminate the temperature variation of kt/q , this differ ence voltage is applied to a processing block essentially an analog divider that effectively puts a variable proportional to temperature underneath the t in equation 10. in this same block, i ref is trans- formed to the much smaller current i z , to provide the previously defined value for v log , that is, vv ii log y pd z = log ( / ) 10 (11) recall that v y is 200 mv/decade and i z is 100 pa. internally, this is generated first as an output current of 40 a/decade (2 a/db) applied to an internal load resistor from vlog to acom that is laser-trimmed to 5 k ? 1%. the slope may be altered at this point by adding an external shunt resistor. this is required when using the minimum supply voltage of 3.0 v, because the span of v log for the full 160 db (eight-decade) range of i pd amounts to 8 0.2 v = 1.6 v, which exceeds the internal headroom at this node. using a shunt of 5 k ? , this is reduced to 800 mv, that is, the slope becomes 5 mv/db. in those applications needing a higher slope, the buffer can provide voltage gain. for example, to raise the output swing to 2.4 v, which can be accommodated by the rail-to-rail buffer when using a 3.0 v supply, a gain of 3 can be used which raises the slope to 15 mv/db. slope variations implemented in these ways do not affect the intercept. keep in mind these measures to address the limitations of a small positive supply voltage will not be needed when i pd is limited to about 1 ma maximum. they can also be avoided by using a negative supply that allows v log to run below ground, which will be discussed later. figure 1 shows how a sample of the input current is derived using a very small monitoring transistor, q m , connected in parallel with q1. this is used to generate the photodiode bias, v pdb , at pin v pdb , which varies from 0.6 v when i pd = 100 pa, and reverse-biases the diode by 0.1 v (after subtracting the fixed 0.5 v at inpt ) and rises to 2.6 v at i pd = 10 ma, for a net diode bias of 2 v. the driver for this output is current-limited to about 20 ma. the system is completed by the final buffer amplifier, which is essentially an uncommitted op amp with a rail-to-rail output capability, a 10 mhz bandwidth, and good load-driving capabili- ties, and may be used to implement multipole low-pass filters, and a voltage reference for internal use in controlling the scaling, but that is also made available at the 2.0 v level at pin vref. figure 2 shows the ideal output v log versus i pd . bandwidth and noise considerations the response time and wide-band noise of translinear log amps are fundamentally a function of the signal current i pd . the bandwidth becomes progressively lower as i pd is reduced, largely due to the effects of junction capacitances in q1. this is easily understood by noting that the transconductance ( g m ) of a bipolar transistor is a linear function of collector current, i c , (hence, translinear), which in this case is just i pd . the corre- sponding incremental emitter resistance is: r kt qi e pd == 1 g m (12) basically, this resistance and the capacitance c j of the transistor generate a time constant of r e c j and thus a corresponding low-pass corner frequency of: f qi ktc db pd j 3 2 = (13) showing the proportionality of bandwidth to current.
rev. a C10C ad8304 input ?a 100p 10m 1n 10n 100n 1 10 100 1m 1.6 v log ?v 0.8 0 0.4 1.2 figure 2. ideal form of v log vs. i pd using a value of 0.3 pf for c j evaluates to 20 mhz/ma. there- fore, the minimum bandwidth at i pd = 100 pa would be 2 khz. while this simple model is useful in making a point, it excludes other effects that limit its usefulness. for example, the network r1, c1 in figure 1, which is necessary to stabilize the system over the full range of currents, affects bandwidth at all values of i pd . later signal processing blocks also limit the maximum value. tpc 7 shows ac response curves for the ad8304 at eight repre- sentative currents of 100 pa to 10 ma, using r 1 = 750 ? and c 1 = 1000 pf. the values for r1 and c1 ensure stability over the full 160 db dynamic range. more optimal values may be used for smaller subranges. a certain amount of experimental trial and error may be necessary to select the optimum input network component values for a given application. turning now to the noise performance of a translinear log amp, the relationship between i pd and the voltage noise spectral density, s nsd , associated with the v be of q1, evaluates to the following: s i nsd pd = 14 7 . (14) where s nsd is nv/hz, i pd is expressed in microamps and t a = 25 c. for an input of 1 na, s nsd evaluates to almost 0.5 v/ hz; assum- ing a 20 khz bandwidth at this current, the integrated noise voltage is 70 v rms. however, the calculation is not complete. the basic scaling of the v be is approximately 3 mv/db; translated to 10 mv/db, the noise predicted by equation 14 must be multi- plied by approximately 3.33. the additive noise effects associated with the reference transistor, q2, and the temperature compen- sation circuitry must also be included. the final voltage noise spectral density presented at the vlog pin varies inversely with i pd , but not as simple as square root. tpc s 8 and 9 show the measured noise spectral density versus frequency at the vlog output, for the same nine-decade spaced values of i pd . chip enable the ad8304 may be powered down by taking the pwdn pin to a high logic level. the residual supply current in the disabled mode is typically 60 a. using the ad8304 the basic connections (figure 3) include a 2.5:1 attenuator in the feedback path around the buffer. this increases the basic slope of 10 mv/db at the vlog pin to 25 mv/db at v out . for the full dynamic range of 160 db (80 db optical), the output swing is thus 4.0 v, which can be accommodated by the rail-to-rail output stage when using the recommended 5 v supply. the capacitor from vlog to ground forms an optional single- pole low-pass filter. since the resistance at this pin is trimmed to 5 k ? , an accurate time constant can be realized. for ex- ample, with c flt = 10 nf, the C 3 db corner frequency is 3.2 khz. such filtering is useful in minimizing the output noise, particularly when i pd is small. multipole filters are more effec- tive in reducing noise, and are discussed below. a capacitor between vsum and ground is essential for minimizing the noise on this node. when the bias voltage at either vpdb or vref is not needed these pins should be left unconnected. slope and intercept adjustments the choice of slope and intercept depends on the application. the versatility of the ad8304 permits optimal choices to be made in two common situations. first, it allows an input current range of less than the full 160 db to use the available voltage span at the output. second, it allows this output voltage range to be optimally positioned to fit the input capacity of a subsequent adc. in special applications, very high slopes, such as 1 v/dec, allow small subranges of i pd to be covered at high sensitivity. the slope can be lowered without limit by the addition of a shunt resistor, r s , from vlog to ground. since the resistance at this pin is trimmed to 5 k ? , the accuracy of the modified slope will depend on the external resistor. it is calculated using: v vr rk y ys s = + '5 ? (15) 3 4 pdb bias vref 10 2 12 vpdb vsum inpt vsum 5 1 vneg ~ 10k a com 14 vps2 pwdn vps1 vref 7 vlog 8 bfin 9 bfng temperature compensation 5k 11 v out 0.5v i pd nc r1 750 10nf c1 1nf 13 ra 15k rb 10k cflt 200mv/dec v p v out 500mv/dec nc = no connect figure 3. basic connections (ra, rb, cflt are optional; r1 and c1 are the default values) for example, using r s = 3 k ? , the slope is lowered to 75 mv per decade or 3.75 mv/db. table i provides a selection of suitable values for r s and the resulting slopes. table i. examples of lowering the slope r s (k )v y (mv/dec) 375 5 100 15 150
rev. a ad8304 ?11? in addition to uses in filter and comparator functions, the buffer amplifier provides the means to adjust both the slope and inter- cept, which require a minimal number of external components. the high input impedance at bfin, low input offset voltage, large output swing, and wide bandwidth of this amplifier permit numerous transformations of the basic v log signal, using stan- dard op amp circuit practices. for example, it has been noted that to raise the gain of th e buffer, and th erefore t he slope, a feedback attenuator, r a and r b in figure 3, should be inserted between vlog and the inverting input pin bfng. a wide range of gains may be used and the resistor magnitudes are not critical; their parallel sum should be about equal to the net source resistance at the noninverting input. when high gains are used, the output dynamic range will be reduced; for maxi- mum swing of 4.8 v, it will amount to simply 4.8 v/v y decades. thus, using a ratio of 3 , to set up a slope 30 mv/db (600 mv/ decade), eight decades can be handled, while with a ratio of 5 , which sets up a slope of 50 mv/db (1 v/decade), the dynamic range is 4.8 decades, or 96 db. when using a lower positive supply voltage, the calculation proceeds in the same way, re membering to first subtract 0.2 v to allow for 0.1 v upper and lower headroom in the output swing. alteration of the logarithmic intercept is only slightly more tricky. first note that it will rarely be necessary to lower the intercept below a value of 100 pa, since this merely raises all output volt- ages further above ground. however, where this is required, the first step is to raise the voltage v log by connecting a resistor, r z , from vlog to vref (2 v) as shown in figure 4. 6 3 4 pdb bias vref 10 2 12 vpdb vsum inpt vsum 5 1 vneg ~ 10k a com 14 vps2 pwdn vps1 vref 7 vlog 8 bfin 9 bfng temperature compensation 5k 11 v out 0.5v i pd nc r1 750 10nf c1 1nf 13 ra v p v out nc = no connect rb rz figure 4. method for lowering the intercept this has the effect of elevating v log for small inputs while lower- ing the slope to some extent because of the shunt effect of r z on the 5 k output resistance. then, if necessary, the slope may be increased as before, using a feedback attenuator around the buffer. table ii lists some examples of lowering the intercept combined with various slope variations. table ii. examples of lowering the intercept v y (mv/decade) i z (pa) r a (k )r b (k )r z (k ) 200 1 20.0 100 25 200 10 10.0 100 50 200 50 3.01 100 165 300 1 10.0 12.4 25 300 10 8.06 12.4 50 300 50 6.65 12.4 165 400 1 11.5 8.2 25 400 10 9.76 8.2 50 400 50 8.66 8.2 165 500 1 16.5 8.2 25 500 10 14.3 8.2 50 500 50 13.0 8.2 165 equations for use with table ii: vgv r rr i i v r rr out y z z log pd z ref log log z = +
+ + log 10 where g r r rk a b log =+ = 15 and generally, it will be useful to raise the intercept. keep in mind that this moves the v log line in figure 2 to the right, lowering all output values. figure 5 shows how this is achieved. the feedback resistors, r a and r b , around the buffer are now augmented with a third resistor, r z , placed between the pins bfng and vref. this raises the zero-signal voltage on bfng, which has the effect of pushing v out lower. note that the addition of this resistor also alters the feedback ratio. however, this is readily compensated in the design of the network. table iii lists the resistor values for representative intercepts. table iii. examples of raising the intercept v y (mv/decade) i z (na) r a (k )r b (k )r c (k ) 300 10 7.5 37.4 24.9 300 100 8.25 130 18.2 400 10 10 16.5 25.5 400 100 9.76 25.5 16.2 400 500 9.76 36.5 13.3 500 10 12.4 12.4 24.9 500 100 12.4 16.5 16.5 500 500 11.5 20.0 12.4 equations for use with table iii: vgv i i v rr rr r out y pd z ref ab ab c =
+ log ? 10 where g r rr rr rr rr a bc ab ab ab =+ = + 1 and
rev. a C12C ad8304 6 3 4 pdb bias vref 10 2 12 vpdb vsum inpt vsum 5 1 vneg ~ 10k a com 14 vps2 pwdn vps1 vref 7 vlog 8 bfin 9 bfng temperature compensation 5k 11 v out 0.5v i pd nc r1 750 10nf c1 1nf 13 ra v p v out nc = no connect rb rc figure 5. method for raising the intercept low supply slope and intercept adjustment when using the device with a positive supply less than 4 v, it is necessary to reduce the slope and intercept at the vlog pin in order to preserve good log conformance over the entire 160 db operating range. the voltage at the vlog pin is generated by an internal current source with an output current of 40 a/decade feeding the internal laser-trimmed output resistance of 5 k ? . when the voltage at the vlog pin exceeds v p C 2.3 v, the current source ceases to respond linearly to logarithmic increases in current. this headroom issue can be avoided by reducing the logarithmic slope and intercept at the vlog pin. this is accomplished by connecting an external resistor r s from the vlog pin to ground in combination with an intercept lowering resistor r z . the values shown in figure 6 illustrate a good solution for a 3.0 v positive supply. the resulting logarithmic slope measured at vlog is 62.5 mv/decade with a new intercept of 57 fa. the original logarithmic slope of 200 mv/decade can be recovered using voltage gain on the internal buffer amplifier. 6 3 4 pdb bias vref 10 2 12 vpdb vsum inpt vsum 5 1 vneg ~ 10k a com 14 vps2 pwdn vps1 vref 7 vlog 8 bfin 9 bfng temperature compensation 5k 11 v out 0.5v i pd nc r1 750 10nf c1 1nf 13 ra 4.98k v p v out nc = no connect rb 2.26k rs 2.67k rz 15.4k 62.5mv/dec figure 6. recommended low supply application circuit using the adaptive bias for most photodiode applications, the placement of the anode somewhat above ground is acceptable, as long as the positive bias on the cathode is adequate to support the peak current for a particular diode, limited mainly by its series resistance. to address this matter, the ad8304 provides for the diode a bias that varies linearly with the current. this voltage appears at pin vpdb, and varies from 0.6 v (reverse-biasing the diode by 0.1 v) for i pd = 100 pa and rises to 2.6 v (for a diode bias of 1 v) at i pd = 10 ma. this results in a constant internal junction bias of 0.1 v when the series resistance of the photodiode is 200 ? . for optical power measurements over a wide dynamic range the adaptive biasing function will be valuable in minimizing dark current while pre- venting the loss of photodiode bias at high currents. use of the adaptive bias feature is shown in figure 7. 6 3 4 pdb bias vref 10 2 12 vpdb vsum inpt vsum 5 1 vneg ~ 10k a com 14 vps2 pwdn vps1 vref 7 vlog 8 bfin 9 bfng temperature compensation 5k 11 v out 0.5v i pd cpb r1 750 10nf c1 1nf 13 ra rb cfilt v p v out figure 7. using the adaptive biasing capacitor cpb, between the photodiode cathode at pin vpdb and ground, is included to lower the impedance at this node and thereby improve the high frequency accuracy at those current levels where the ad8304 bandwidth is high. it also ensures an hf path for any high frequency modulation on the optical signal which might not otherwise be accurately averaged. it will not be necessary in all cases, and experimentation may be required to find an optimum value. changing the voltage at the summing node the default value of vsum is determined by using a quarter of vref (2 v). this may be altered by applying an independent volt- age source to vsum, or by adding an external resistive divider from vref to vsum. this network will operate in parallel with the internal divider (40 k ? and 13.3 k ? ), and the choice of external resistors should take this into account. in practice, the total resistance of the added string may be as low as 10 k ? (consuming 400 a from vref). low values of vsum and thus v ce (see figure 13) are not advised when large values of i pd are expected. implementing low-pass filters noise, leading to uncertainty in an observed value, is inherent to all measurement systems. translinear log amps exhibit significant amounts of noise for reasons stated above, and are more trouble- some at low current levels. the standard way of addressing this problem is to average the measurement over an appropriate time interval. this can be achieved in the digital domain, in post-adc dsp, or in analog form using a variety of low-pass structures.
rev. a ad8304 C13C the use of a capacitor at the vlog pin to create a single-pole filter has already been mentioned. the small added cost of the few external components needed to realize a multipole filter is often justified in a high performance measurement system. figure 8 shows a sallen-key filter structure. here, the resistor needed at the front of the network is provided entirely by the accurate 5 k ? present at the vlog output; r b will have a similar value. the corner frequency and q (damping factor) are determined by the capacitors c a and c b and the gain g = (r a + r b )/r b . a suggested starting point for choosing these components using various gains is pro- vided in table iv; the values shown are for a 1 khz corner ( also see tpc 12). this frequency can be increased or decreased by scaling the capacitor values. note that r d , g, and the capacitor ratio c a /c b should not deviate from the suggested values to maintain the shape of the ac amplitude re sponse and pulse overshoot provided by the values shown in this table. in all cases, the roll-off rate above the corner is 40 db/dec. 6 3 4 pdb bias vref 10 2 12 vpdb vsum inpt vsum 5 1 vneg ~ 10k a com 14 vps2 pwdn vps1 vref 7 vlog 8 bfin 9 bfng temperature compensation 5k 11 v out 0.5v i pd nc r1 750k 10nf c1 1nf 13 ra v p v out nc = no connect ca rd rb cb figure 8. two-pole low-pass filter table iv. two-pole filter parameters for 1 khz cutoff frequency * r a r b v y r d c a c b (k )(k )g (v/decade) (k ) (nf) (nf) 0 open 1 0.2 11.3 12 12 10 10 2 0.4 6.02 33 22 12 8 2.5 0.5 12.1 33 18 24 6 5 1.0 10.0 33 18 the corner frequency can be adjusted by scaling capacitors c a and c b . for example, to reduce the corner frequency to 100 hz, raise the values of c a and c b by 10 . *see tpc 12. operation in comparator modes in certain applications, the need may arise to generate a logical output when the input current has reached a certain value. this can be easily addressed by using a fraction of the voltage refer- ence to provide the setpoint (threshold) and using the buffer without feedback in a comparator mode, as illustrated in figure 9. since v log runs from ground up to 1.6 v maximum, the 2 v reference is more than adequate to cover the full dynamic range of i pd . note that the threshold for an increasing i pd is un changed, while the release point for decreasing currents is 5 db below this. raising r h to 5 m ? reduces the hysteresis to 0.5 db, or it may be increased using a lower value for r h . 6 3 4 pdb bias vref 10 2 12 vpdb vsum inpt vsum 5 1 vneg ~ 10k a com 14 vps2 pwdn vps1 vref 7 vlog 8 bfin 9 bfng temperature compensation 5k 11 v out 0.5v i pd nc r1 750 10nf c1 1nf 13 v p nc = no connect rh rg ra v out figure 9. using the buffer as a comparator using a negative supply most applications of the ad8304 will require only a single supply of 3.0 v to 5.5 v. however, to provide further versatility, dual supplies may be employed, as illustrated in figure 10. the use of a negative supply, v n , allows the summing node to be placed exactly at ground level, because the input transistor (q1 in figure 1) will have a negative bias on its emitter. v n may be as small as ? 0.5 v, making the v ce the same as for the default case. this bias need not be accurate, and a poorly defined source can be used. a larger supply of up to ? 5v may be used. the effect on scaling is minor. it merely moves the intercept by ~0.01 db/v. accord- ingly, an uncertainty of 0.2 v in v n would result in a negligible error of 0.002 db. the slope is unaffected by v n . the log lin- earity will be degraded at the extremes of the dynamic range as indicated in figure 11. the bias current, buffer output (and its load) current, and the full i pd all have to be absorbed by this negative supply, and its supply capacity must be ensured for the maximum current condition. 6 3 4 pdb bias vref 10 2 12 vpdb vsum inpt vsum 5 1 vneg ~ 10k a com 14 vps2 pwdn vps1 vref 7 vlog 8 bfin 9 bfng temperature compensation 5k 11 v out 0.5v i pd nc r1 750 c1 1nf 13 v p nc = no connect rb ra v out v n ( ?.5v to ?v) figure 10. using a negative supply with the summing node at ground, the ad8304 may now be used as a voltage-input log amp, simply by inserting a suitably scaled resistor from the voltage source to the inpt pin. the logarith- mi c accuracy for small voltages is limited by the offset of the jfet op amp, appearing between this pin and vsum. the use of a negative supply also allows the output to swing below ground, thereby allowing the intercept to correspond to a midrange value of i pd . however, the voltage v log remains referenced to the
rev. a C14C ad8304 acom pin, and does not normally go negative with regard to this pin, but is free to do so. therefore, a resistor from vlog to the negative supply can lower v log , thus raising the intercept. a more accurate method for repositioning the intercept is described below. input ?a 100p 10m 1n 10n 100n 1 10 100 1m 2.0 ?.0 error ?db (10mv/db) 1.5 0 ?.5 ?.0 ?.5 1.0 0.5 without intercept adjust with intercept adjust v neg = 0 v neg = ?.5 v neg = ? figure 11. log conformance (linearity) vs. i pd for various negative supplies applications the ad8304 incorporates features that improve its usefulness in both fiber optic supervisory applications and in more general ones. to aid in the exploration of these possibilities, a spice macro- model is provided and a versatile evaluation board is available. the macromodel is shown in generalized schematic form (and thus is independent of variations in spice programs) in figure 12. q1, qm, and q2 (here made equal in size) correspond to the identical transistors in figure 1. the model parameters for these transistors are not critical; the default model provided in spice libraries will be satisfactory. however, the ad8304 employs compensation techniques to reduce errors caused by junction resistances (notably, rb and re) at high input currents. there- fore, it is advisable to set these to zero. while this will not model the ad8304 precisely, it is safer than using possibly high default values for these parameters. the low current model parameters may also need consideration. note that no attempt is made to capture either dynamic behavior or the effects of temperature in this simple macromodel; scaling is correct for 27 c. v e4 v2 r1 r2 vlog 7 5 c2 v v1 + q3 i1 ipd in 1 2 3 4 i1 i2 e3 e2 c1 6 rl i1 c1 e1 v1 q1 i2 q2 i3 q3 .model e2 e3 e4 v2 r1 c2 r2 rl 0 in 2 1 in 0 3 0 4 npn 5 6 7 8 8 9 9 vlog in 0 0 0 2 3 3 4 4 npn 0 0 0 7 9 0 vlog 0 dc 1.0n in 0.5 0 1 0 316.2 0 poly (2) poly (2) 6 5 100k 0.8 100 163p 4.9k 1000k 1 a 1 npn npn npn 2 3 1 0 0, 0, 0, 0, 1 4 3 7 0 0, 0, 0, 0, 1 3k q2 q1 100k 3k + figure 12. basic macromodel
rev. a ad8304 C15C summing node at ground and voltage inputs a negative supply may be used to reposition the input node at ground potential. a voltage as small as C 0.5 v is sufficient. figure 13 shows the use of this feature. an input current of up to 10 ma is supported. this connection mode will be useful in cases where the source is a positive voltage v sig referenced to ground, rather than for use with photodiodes, or other perfect current sources. r in scales the input current and should be chosen to optimally position the range of i pd , or provide a very high input resistance, thus minimizing the loading of the signal source. for example, assume a voltage source that spans the four-decade range from 100 mv to 1 kv and is desired to maximize r in . when set to 1 g ? , i pd spans the range 100 pa to 1 ma. using a value of 10 m ? , the same four decades of input voltage would span the central current range of 10 na to 100 ma. smaller input voltages can be measured accurately when aided by a small offset-nulling voltage applied to vsum. the optional network shown in figure 13 provides more than 20 mv for this purpose. 6 3 4 pdb bias vref 10 2 12 vpdb vsum inpt vsum 5 1 vneg ~ 10k a com 14 vps2 pwdn vps1 vref 7 vlog 8 bfin 9 bfng temperature compensation 5k 11 v out 0.5v nc 13 v p nc = no connect rb ra v out rin v sig 1k 10k v p v n v low i pd ad8304 figure 13. using a negative supply and placing vsum at ground permits voltage-mode inputs the minimum voltage that can be accurately measured is then limited only by the drift in the input offset of the ad8304. the specifications show the maximum spread over the full tempera- ture and supply range. over a limited temperature range, and with a regulated supply, the offset drift will be lower; in this situation, processing of inputs down to 5 mv is practicable. the input system of the ad8304 is quasi-differential, so vsum can be placed at an arbitrary reference level v low , over a wide range, and used as the signal lo of the source. for example, using v p = 5 v and v n = C 3 v, v low can be any voltage within a 2.5 v range. providing negative outputs and rescaling as noted, the ad8304 allows the buffer to drive a load to negative voltages with respect to acom, the analog common pin, which is grounded. a negative supply capable of supporting the input current i pd must be used, the fraction of quiescent bias that flows out of the vneg pin, and the load current at vlog. for the example shown in figure 14, this totals less than 20 ma when driving a 1 k ? load as far as C 4v. the use of a much larger value for the intercept may be useful in certain situations. in this example, it has been moved up four decades, from the default value of 100 pa to the center of the full eight-decade range at 1 ma. using a voltage input as described above, this corresponds to an altered voltage-mode intercept, v z , which would be 1 v for r in = 1 m ? . to take full advantage of the larger output swing, the gain of the buffer has been increased to 4.53, resulting in a scaling of 900 mv/decade and a full-scale output of 3.6 v. 6 3 4 pdb bias vref 10 2 12 vpdb vsum inpt vsum 5 1 vneg ~ 10k a com 14 vps2 pwdn vps1 vref 7 vlog 8 bfin 9 bfng temperature compensation 5k 11 v out 0.5v nc 13 v p nc = no connect rb 22.6k ra 13.3k v out rin v sig 1k 10k v p v n v low i pd rl 1k rc 12.4k ad8304 figure 14. using a negative supply to allow the output to swing below ground inverting the slope the buffer is essentially an uncommitted op amp that can be used to support the operation of the ad8304 in a variety of ways. it can be completely disconnected from the signal chain when not needed. figure 15 shows its use as an inverting amplifier; this changes the polarity of the slope. the output can either be repositioned to all positive values by applying a fraction of v ref to the bfin pin, or range negative when using a negative supply. the full design for a practical application is left undefined in this brief illustration, but a few cases will be discussed. for example, suppose we need a slope of C 30 mv/db; this requires the gain to be three. since v log exhibits a source resistance of 5k ? , r b must be 15 k ? . in cases where a small negative supply is available, the output voltage can swing below ground, and the bfin pin may be grounded. but a negative slope is still possible when only a single supply is used; a positive offset, v ofs , is applied to this pin, as indicated in figure 15. in general, the resulting output voltage can be expressed as: v r k v i i v out b y pd z ofs = ? ? ? ? ? ? ? ? ? ? ? ? + C log 5 10 ? (16)
rev. a C16C ad8304 6 3 4 pdb bias vref 10 2 12 vpdb vsum inpt vsum 5 1 vneg ~ 10k a com 14 vps2 pwdn vps1 vref 7 vlog 8 bfin 9 bfng temperature compensation 5k 11 v out 0.5v i pd nc r1 750 c1 1nf 13 v p nc = no connect rb v out v n ( ?.5v to ?v) 10nf v ofs ad8304 figure 15. using the buffer to invert the polarity of the slope when the gain is set to 13 (r b = 5 k ? ) the 2 v v ref can be tied directly to bfin, in which case the starting point for the output response is at 4 v. however, since the slope in this case is only C 0.2 v/decade, the full current range will only take the output down by 1.6 v. clearly, a higher slope (or gain) is desirable, in which case v ofs should be set to a smaller voltage to avoid railing the output at low currents. if v ofs = 1.2 v and g = 33, vout now starts at 4.8 v and falls through this same voltage toward ground with a slope of C 0.6 v per decade, spanning the full range of i pd . programmable level comparator with hysteresis the buffer amplifier and reference voltage permit a calibrated level detector to be realized. figure 16 shows the use of a 10-bit mdac to control the setpoint to within 0.1 db of an exact value over the 100 db range of 1 na i pd 100 a when the full- scale output of the mdac is equal to that of its reference. the 2 v v ref also sets the minimum value of v spt to 0.2 v, correspond- ing to an input of 1 na. since 100 db at the vlog interface corresponds to a 1 v span, the resistor network is calculated to provide a maximum v spt of 1.2 v while adding the required 10% of v ref . in this example, the hysteresis range is arranged to be 0.1 db, (1 mv at vlog) when using a 5 v supply. this will usually be adequate to prevent noise that causes the comparator output to thrash. that risk can be reduced further by using a low-pass filtering capacitor at v log (shown dotted) to decrease the noise bandwidth. 6 3 4 pdb bias vref 10 2 12 vpdb vsum inpt vsum 5 1 vneg ~ 10k a com 14 vps2 pwdn vps1 vref 7 vlog 8 bfin 9 bfng temperature compensation 5k 11 v out 0.5v i pd nc 750 1nf 13 v p nc = no connect 50m v out 10nf v spt vref v out m dac 49.9k 100k rh ad8304 figure 16. calibrated level comparator 6 3 4 pdb bias vref 10 2 12 vpdb vsum inpt vsum 5 1 vneg ~ 10k a com 14 vps2 pwdn vps1 vref 7 vlog 8 bfin 9 bfng temperature compensation 5k 11 v out 0.5v i src 25k nc 13 v p nc = no connect c2 1nf v n (?.5v to ?v) 1k vref v out m dac c1 10nf 100k ad8304 figure 17. multidecade current source
rev. a ad8304 ?17? programmable multidecade current source the ad8304 supports a wide variety of general (nonoptical) applications. for example, the need frequently arises in test equipment to provide an accurate current that can be varied over many decades. this can be achieved using a logarithmic amplifier as the measuring device in an inverse function loop, as illustrated in figure 16. this circuit generates the current: ipa src v spt = () 100 10 02 /. (17) the principle is as follows. the current in qa is forced to supply a certain i pd by measuring the error between a setpoint v spt and v log , and nulling this error by integration. this is performed by the internal op amp and capacitor c1, with a time constant formed with the internal 5 k ? resistor. the choice of c1 in this example ensures loop stability over the full eight-decade range of output currents; c2 reduces phase lag. the system is completed with a 10-bit mdac using v ref as its reference, whose output is scaled to 1.6 v fs by r1 and r2 (whose parallel sum is also 5 k ? ). transistor qa may be a single bipolar device, which will result in a small alpha error in i src (the current is monitored in the emitter branch), or a darlington pair or an mos device, either of which ensure a negligible difference between i pd and i src . in this example, the bipolar pair is used. the output voltage compliance is deter- mined by the collector breakdown voltage of these transistors, while the minimum voltage depends on where vsum is placed. optional components could be added to put this node and vneg at a low enough bias to allow the voltage to go slightly below ground. many variations of this basic circuit are possible. for example, the current can be continuously controlled by a simple voltage, or by a second current. larger output currents can be controlled by setting v sum to zero and using a current shunt divider. characterization setups and methods during the primary characterization of the ad8304, the device was treated as a high precision current-in logarithmic amplifier (converter). rather than attempting to accurately generate photo- currents by illuminating a photodiode, precision current sources, like the keithley 236, were used as input sources. great care was taken when applying the low level input currents. the triax output of the current source was used with the guard connected to vsum at the characterization board. on the board the input trace was guarded by connecting adjacent traces and a portion of an internal copper layer to the vsum pins. one obvious reason for the care was leakage current. with 0.5 v as the nominal bias on the inpt pin, a resistance of 50 g ? to ground would cause 10 pa of leakage, or about one decibel of error at the low end of the measurement range. additionally, the high output resistance of the current source and the long signal cable lengths commonly needed in characterization make a good receiver for 60 hz emis- sions. good guarding techniques help to reduce the pickup of unwanted signals. keithley 236 inpt pwdn vneg vpos vsum vpdb vref v out bfin vlog ad8304 characterization board triax connector * * signal: inpt; guard: vsum; shield: ground dc matrix, dc supplies, dmm ribbon cable figure 18. primary characterization setup the primary characterization setup shown in figure 18 is used to measure the static performance, logarithmic conformance, slope and intercept, buffer offset and v ref drift with temperature, and the performance of the vpdb pin functions. for the dynamic tests, such as noise and bandwidth, more specialized setups are used. ad8138 evaluation board output input inputa hp 3577a network analyzer inputb +in b a vneg pwdn vsum inpt vsum vpdb vref a com bfng vps1 v out vps2 bfin vlog 1 2 3 4 5 6 7 14 13 12 11 10 9 8 power splitter 49.9 0.1 f +v s ad8304 figure 19. configuration for buffer amplifier bandwidth measurement figure 19 shows the configuration used to measure the buffer amplifier bandwidth. the ad8138 evaluation board provides a dc offset at the buffer input, allowing measurement in single-supply mode. the network analyzer input impedance was set to 1 m ? .
rev. a C18C ad8304 1 vneg acom 14 2 pwdn bfng 13 3 vsum vps1 12 4 inpt vout 11 5 vsum vps2 10 6 vpdb bfin 9 7 vref vlog 8 c2 1nf c1 0.1nf r10 10k +v s ? s gnd sw1 r5 open r7 open lk1 installed input biaser lk2 open c10 0.1 f c11 1nf r15 750 r7 open r9 0.1 f r6 open c9 10nf r4 open r3 open r1 open r2 0 c3 1nf c4 0.1 f r11 0 r14 0 c6 open c5 open c7 open r12 open c8 open r13 0 bu ffer out log out ad8304 figure 22. evaluation board schematic ad8138 evaluation board output input inputa hp 3577a network analyzer inputb +in b a vneg pwdn vsum inpt vsum vpdb vref a com bfng vps1 v out vps2 bfin vlog 1 2 3 4 5 6 7 14 13 12 11 10 9 8 power splitter 0.1 f r1 750 1nf +v s ad8304 figure 20. configuration for logarithmic amplifier bandwidth measurement the setup shown in figure 20 was used for frequency response measurements of the logarithmic amplifier section. in this con- figuration, the ad8138 output was offset to 1.5 v and r1 was adjusted to provide the appropriate operating current. the buffer amplifier was then used; still any capacitance added at the vlog pin during measurement would form a filter with the on-chip 5 k ? resistor. the configuration illustrated in figure 21 measures the device noise. batteries provide both the supply and the input signal to remove the supplies as a possible noise source and to reduce ground loop effects. the ad8304 evaluation board and the current setting resistors are mounted in closed aluminum enclo- sures to provide additional shielding to external noise sources. source trigger channel 1 hp 89410a channel 2 vneg pwdn vsum inpt vsum vpdb vref a com bfng vps1 v out vps2 bfin vlog 1 2 3 4 5 6 7 14 13 12 11 10 9 8 r1 750 1nf alkaline d cell alkaline d cell ad8304 figure 21. configuration for noise spectral density measurement evaluation board an evaluation board is available for the ad8304, the schematic for which is shown in figure 22, and the two board sides are shown in figure 23 and figure 24. it can be configured for a wide variety of experiments. the board is factory set for photocon- ductive mode with a buffer gain of unity, providing a slope of 10 mv/db and an intercept of 100 pa. by substituting resistor and capacitor values, all of the application circuits presented in this data sheet can be evaluated. table v describes the various configu- ration options.
rev. a ad8304 C19C table v. evaluation board configuration options component function default condition v p , v n , agnd positive and negative supply and ground pins not applicable sw1, r10 device enable: when sw1 is in the 0 position, the pwdn pin is sw1 = installed connected to ground and the ad8304 is in its normal operating mode. r10 = 10 k ? (size 0603) r1, r2 buffer amplifier gain/slope adjustment: the logarithmic slope r1 = open (size 0603) of the ad8304 can be altered using the buffer s gain-setting resistors, r2 = 0 ? (size 0603) r1 and r2. r3, r4 intercept adjustment: a dc offset can be applied to the input term- r3 = open (size 0603) inals of the buffer amplifier to adjust the effective logarithmic intercept. r4 = open (size 0603) r5, r6, r7, r8, r9 bias adjustment: the voltage on the vsum and inpt pins can be r5 = r6 = open (size 0603) altered using appropriate resistor values. r9 is populated with a decoup- r7 = r8 = open (size 0603) ling capacitor to reduce noise pickup. the decoupling capacitor can be r9 = 0.1 f (size 0603) removed when a fixed bias is applied to vsum. c1, c2, c3, c4, c9 supply decoupling capacitors c1 = c4 = 0.1 f (size 0603) c2 = c3 = 1 nf (size 0603) c9 = 10 nf (size 0603) c10 photodiode biaser decoupling: provides high frequency decoupling c10 = 0.1 f (size 0603) of the adaptive bias output at pin vpdb. c5, c6, c7, c8, r11, output filtering: allows implementation of a variety of filter config- r11 = r13 = 0 ? (size 0603) r12, r13, r14 urations, from simple rc low-pass filters to three-pole sallen and key. r12 = open (size 0603) c7 = c8 = open (size 0603) r15, c11 input filtering: provides essential hf compensation at the input r15 = 750 ? (size 0603) pin inpt. c11 = 1 nf (size 0603) lk1, lk2 guard/shield options: the shells of the sma connectors used lk1 = installed for the input and the photodiode bias can be set to the voltage on the lk2 = open vsum pin or connected to ground. figure 23. component side layout figure 24. component side silkscreen r14 = 0 ? (size 0603) c5 = c6 = open (size 0603)
c02743C0C8/02(a) printed in u.s.a. C20C ad8304 rev. a outline dimensions 14-lead thin shrink small outline package [tssop] (ru-14) dimensions shown in millimeters 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc seating plane 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 8 0 0.75 0.60 0.45 compliant to jedec standards mo-153ab-1 revision history location page 8/02?ata sheet changed from rev. 0 to rev. a. edits to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 new tpc 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 edits to tpc 7 caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 changes to tpc 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 edits to using the ad8304 section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 changes to figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 edits to table i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 edits to table iii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 new figure 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 changes to figure 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 changes to table v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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